--
-- VHDL Architecture Fietscomputer_lib.fc_63_to_49.behavioural
--
-- Created:
--          by - 10070052.UNKNOWN (DTP7810)
--          at - 09:51:01 22-09-2011
--
-- using Mentor Graphics HDL Designer(TM) 2008.1b (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY fc_63_to_49 IS
GENERIC( 
    size_in  : NATURAL := 20;
    size_out : NATURAL := 12
);
   PORT (
      input : IN     STD_LOGIC_VECTOR(size_in -1 DOWNTO 0);
      uit   : OUT    STD_LOGIC_VECTOR(size_out -1 DOWNTO 0)
   );
END fc_63_to_49;

--
ARCHITECTURE behavioural OF fc_63_to_49 IS
BEGIN
  uit <= resize(unsigned(input), uit'size);
END ARCHITECTURE behavioural;

